1. Field of the Invention
The invention pertains generally to a method for fabricating devices, e.g., semiconductor devices, as well as the resulting devices.
2. Art Background
The deposition of metal-containing materials, i.e., pure metals, molecular-type materials in which the molecules include one or more metal atoms, and/or mixtures which include one or more of the above, onto a processed or unprocessed substrate plays a significant role in the fabrication of a variety of devices. Such devices include, for example, discrete semiconductor devices, integrated circuit devices, and magnetic bubble devices. Typically, the deposition of, for example, a pure metal onto selected regions of a processed or unprocessed semiconductor substrate is accomplished by forming a patterned deposition mask, e.g., a patterned photoresist layer, on the substrate surface, and then e-beam evaporating or rf-sputtering the metal onto the mask-bearing substrate surface. Subsequent removal of the mask leaves the metal covering only the selected substrate regions. Alternatively, and without forming a deposition mask, the metal is deposited directly onto the substrate surface, and a patterned etch mask, e.g., a patterned photoresist layer, formed on the metal. Then, the metal is etched through the etch mask, and the etch mask is removed, again leaving metal only in the selected regions.
Included among the integrated circuit devices whose fabrication involves the deposition of metal-containing materials are many MOS (metal-oxide-semiconductor) integrated circuit devices, such as n-channel MOS, p-channel MOS, and CMOS (complementary MOS) integrated circuit devices. (The term integrated circuit, as used herein, denotes a plurality of interconnected, discrete devices.) These MOS integrated circuits (ICs) typically include a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors), each of which includes an active surface layer of semiconductor material, e.g., silicon. Each MOSFET also includes a relatively thin gate oxide (GOX) formed on the surface of the active layer, a conducting gate of, for example, doped polycrystalline silicon (polysilicon), formed on the surface of the GOX, and two relatively heavily doped portions of the active layer, on opposite sides of the gate, which constitute the source and drain of the MOSFET. A relatively thick (compared to the GOX) field oxide (FOX) serves to separate and electrically insulate the MOSFETs from one another.
The MOS ICs, described above, also include metal, e.g., aluminum or aluminum-copper alloy, contacts to, and metal runners extending from, the sources, drains, and gates of the MOSFETs, through which electrical communication is achieved with the MOSFETs. These metal contacts and runners are formed using the deposition and patterning techniques, described above. That is, an electrically insulating glass, e.g., a glass which includes SiO.sub.2 --P.sub.2 O.sub.5 or SiO.sub.2 --P.sub.2 O.sub.5 --B.sub.2 O.sub.3, is first deposited onto the MOSFETs and FOX of an IC using conventional chemical vapor deposition (CVD) techniques, to serve as an interlevel dielectric (an electrically insulating layer) between the gate metallization and the source/drain metallization. Subsequently, the interlevel dielectric is patterned to form via holes to the sources, drains and gates. A metallic conductor, such as aluminum, is deposited, e.g., rf-sputtered or e-beam evaporated, onto the interlevel dielectric, as well as into the via holes, to form the electrical contacts to the sources, drains and gates. The deposited (onto the interlevel dielectric) aluminum is then etched through a patterned etch mask, e.g., a patterned photoresist layer, to form the interconnecting runners which terminate in contact pads.
Significantly, the deposition of metal-containing materials onto device substrates often involves undesirable interactions between the deposited material and the substrates. For example, semiconductor materials, such as silicon, exhibit a relatively high solubility in the deposited metals, such as aluminum, used in the electrical contacts to sources and drains, i.e., the silicon tends to diffuse into the aluminum to form aluminum-silicon alloys. As a consequence, aluminum from the overlying metal contacts diffuses into the underlying silicon to produce what are termed aluminum spikes. As is known, aluminum constitutes a p-type dopant for silicon. Thus, if an aluminum spike were to extend through an n-type source or drain (into a p-type substrate), the p-n junction at the source-substrate or drain-substrate interface would be eliminated. Because aluminum spikes typically extend less than about one micrometer (.mu.m) into silicon, their presence is generally not significant in devices where the source and drain p-n junctions have depths greater than or equal to about 1 .mu.m. Conversely, these spikes pose a serious problem in devices where the p-n junction depths are less than about 1 .mu.m, the very type of devices which, it is expected, will shortly be coming into commercial use.
It has been proposed that aluminum spiking be prevented by replacing aluminum with a silicon-saturated aluminum-silicon alloy, i.e., an alloy which is saturated with silicon at the highest temperature to be encountered during processing. (Such an alloy largely eliminates the silicon concentration gradients at the interfaces between the aluminum and the sources and drains, and thus precludes diffusion of silicon from sources and drains into the metal contacts.) Unfortunately, and subsequent to the high-temperature processing, i.e., at room temperature, these alloys are supersaturated with silicon, which leads to precipitation of silicon (doped with aluminum). Such precipitation, in turn, results in the metal contacts to the n.sup.+ sources and drains (typically doped to a level greater than or equal to about 10.sup.19 cm.sup.-3) exhibiting undesirably high contact resistivities, i.e., contact resistivities higher than about 10.sup.-5 ohm-cm.sup.2, and thus exhibiting undesirably high contact resistances. (By contrast, the contact resistivities to the p.sup.+ sources and drains are only higher than or equal to about 10.sup.-6 ohm-cm.sup.2.)
It has also been proposed that aluminum spiking be prevented, while avoiding high resistance contacts, by providing a barrier to interdiffusion of aluminum and silicon at the sources and drains. It has further been proposed that the barrier be of tungsten (W). One reason for this proposal is that it is known that tungsten can be selectively deposited onto sources and drains, without the use of a patterned deposition mask and without the need for subsequent etching, using either of two low pressure CVD (LPCVD) techniques. In accordance with the first technique, tungsten hexafluoride (WF.sub.6) is flowed over a processed silicon substrate, after the via holes have been formed in the interlevel dielectric but before the aluminum has been deposited into the via holes. Because WF.sub.6 is relatively inert with respect to the SiO.sub.2 of the interlevel dielectric, the WF.sub.6 preferentially reacts with the Si of the exposed source and drain regions to form W (a solid) on these regions and SiF.sub.4 (a gas, exhausted from the reaction chamber) via the overall chemical reaction EQU 2WF.sub.6 +3Si.fwdarw.2W+3SiF.sub.4. (1)
Although this reaction does involve removal (etching) of silicon from the sources and drains, it has always been believed that this is inconsequential. Further, it has been reported that the resulting tungsten layer is typically no more than about 150 Angstroms (.ANG.) thick. Therefore, such a layer would be too thin to serve as an effective diffusion barrier between the aluminum and the silicon.
In accordance with the second technique for selectively depositing tungsten, both WF.sub.6 and H.sub.2 are flowed across the processed silicon substrate (with the total pressure of all the gases within the reaction chamber conventionally maintained at about 1 torr). Initially, the WF.sub.6 reacts with the Si of the exposed sources and drains to form (as discussed above, what is reported to be) a relatively thin layer of W. Then, and provided the deposition temperature is greater than or equal to about 250 degrees Centigrade (C) but less than or equal to about 600 degrees C., it is believed the W covering the exposed source and drain regions, but not the SiO.sub.2 of the interlevel dielectric, serves to catalyze a chemical reaction between the WF.sub.6 and H.sub.2 which yields additional W (formed on the sources and drains) and HF (a gas, exhausted from the reaction chamber) via the overall chemical reaction EQU WF.sub.6 +3H.sub.2 .fwdarw.W+6HF. (2)
While the second technique does produce a sufficiently thick layer of tungsten to act as an effective diffusion barrier, it has been reported that aluminum contacts to (W-covered) p.sup.+ source and drain regions, having depths of about 1 .mu.m, exhibit undesirably high contact resistivities, i.e., contact resistivities higher than or equal to about 10.sup.-5 ohm-cm.sup.2. (The contact resistivities to n.sup.+ sources and drains, having depths of about 1 .mu.m, were reported to be only higher than or equal to about 10.sup.-6 ohm-cm.sup.2.)
Thus, those engaged in the development of device fabrication methods have sought, thus far without success, techniques for forming metal-containing materials on processed or unprocessed substrates which avoid the problems associated with previous such techniques.